The present invention relates to a multi-chip semiconductor device and a chip to be applied to this device and, more particularly, to a multi-chip semiconductor device effective to improve alignment and a chip to be applied to this device.
This application is based on Japanese Patent Application No. 9-109130, filed on Apr. 25, 1997, the content of which is incorporated herein by reference.
Recently, a very large scale integrated circuit (chip) manufactured by integrally forming a number of elements such as transistors and resistors on a semiconductor substrate is often used in an important portion of a computer or a communication apparatus. The performance of this chip is closely related to the performance of a whole apparatus.
On the other hand, a so-called multi-chip semiconductor module has been proposed in which a plurality of chips are stacked to improve the performance of a whole apparatus. Recently, the assignee of the present application has proposed a multi-chip semiconductor device chip, three or more of which can be connected in a small space by a simple method, and a method of forming the chip (U.S. patent application Ser. No. 08/377,486 filed on Aug. 20, 1999.
One characteristic feature of this chip is that a through hole is formed in a semiconductor device on which elements are integrally formed and a connecting plug made of a conductive material is formed in this through hole. Chips are electrically connected via these connecting plugs to accomplish a multi-chip semiconductor device including a plurality of stacked chips.
In this multi-chip semiconductor device, pads made of a conductive material are used to connect connecting plugs of different chips or to electrically connect connecting plugs of different chips and a multilevel interconnecting layer. This pad has a solder bump.
When misalignment between chips is taken into consideration, it is necessary to form a pad having a relatively large area. This is so because the solder bump described above and a connecting plug to be connected to this solder bump are not connected in some cases due to misalignment between the chips. However, forming such pads having a large area is contrary to demanding improved performance by forming pads as many as possible in a chip in order to reduce the parasitic resistance in the interconnecting layer.